List of Supported Instructions

VisUAL supports a small subset of ARM UAL instructions. These are primarily arithmetic, logical, load/store and branch instructions. A short summary of the instruction syntax is given below. For detailed information and examples, press Ctrl+Space when typing an instruction opcode in the code editor.

Summary Opcode Syntax
Move MOV MOV{S}{cond} dest, op1 {, SHIFT_op #expression}
Move Negated MVN MVN{S}{cond} dest, op1 {, SHIFT_op #expression}
Address Load ADR ADR{S}{cond} dest, expression
LDR Psuedo-Instruction LDR LDR{S}{cond} dest, =expression
Add ADD ADD{S}{cond} dest, op1, op2 {, SHIFT_op #expression}
Add with Carry ADC ADC{S}{cond} dest, op1, op2 {, SHIFT_op #expression}
Subtract SUB SUB{S}{cond} dest, op1, op2 {, SHIFT_op #expression}
Subtract with Carry SBC SBC{S}{cond} dest, op1, op2 {, SHIFT_op #expression}
Reverse Subtract RSB RSB{S}{cond} dest, op1, op2 {, SHIFT_op #expression}
Reverse Subtract with Carry RSC RSC{S}{cond} dest, op1, op2 {, SHIFT_op #expression}
Bitwise And AND AND{S}{cond} dest, op1, op2 {, SHIFT_op #expression}
Bitwise Exclusive Or EOR EOR{S}{cond} dest, op1, op2 {, SHIFT_op #expression}
Bitwise Clear BIC BIC{S}{cond} dest, op1, op2 {, SHIFT_op #expression}
Bitwise Or ORR ORR{S}{cond} dest, op1, op2 {, SHIFT_op #expression}
Logical Shift Left LSL LSL{S}{cond} dest, op1, op2
Logical Shift Right LSR LSR{S}{cond} dest, op1, op2
Arithmetic Shift Right ASR ASR{S}{cond} dest, op1, op2
Rotate Right ROR ROR{S}{cond} dest, op1, op2
Rotate Right and Extend RRX RRX{S}{cond} op1, op2
Compare CMP CMP{cond} op1, op2 {, SHIFT_op #expression}
Compare Negated CMN CMN{cond} op1, op2 {, SHIFT_op #expression}
Test Bit(s) Set TST TST{cond} op1, op2 {, SHIFT_op #expression}
Test Equals TEQ TEQ{cond} op1, op2 {, SHIFT_op #expression}
Load Register LDR LDR{B}{cond} dest, [source {, OFFSET}] Offset addressing
LDR{B}{cond} dest, [source, OFFSET]! Pre-indexed addressing
LDR{B}{cond} dest, [source], OFFSET Post-indexed addressing
Store Register STR STR{B}{cond} source, [dest {, OFFSET}] Offset addressing
STR{B}{cond} source, [dest, OFFSET]! Pre-indexed addressing
STR{B}{cond} source, [dest], OFFSET Post-indexed addressing
Load Multiple Registers LDM[dir] LDM[dir]{cond} source, {list of registers}
Store Multiple Registers STM[dir] STM[dir]{cond} dest, {list of registers}
Branch B B{cond} target
Branch with Link BL BL{cond} target
Declare Word(s) in Memory DCD name DCD value_1, value_2, ... value_N
Declare Constant EQU name equ expression
Declare Empty Word(s) in Memory FILL {name} FILL N
N must be a multiple of 4
Stop Emulation END END{cond}

For a comprehensive guide on these instructions and to see examples, browse the ARM Infocenter website here.



The information provided on this page is given on an as is basis, for the purpose of supporting the VisUAL application and its users to debug code. It may be not be up to date with official ARM UAL guidelines at the time you are using it. Always up-to-date information can be found here.